Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon, forming integrated circuits.
Many integrated circuits include a plurality of transistors and other devices formed within and over a substrate, as shown in a cross-sectional view in FIG. 1. The semiconductor device 100 shown includes a workpiece or substrate 102 and transistors 106 that include a gate 108 and source and drain regions 104 formed within the substrate 102. The transistors 106 and other devices (not shown) may be electrically connected together or to other devices using metallization layers M1, V1, and M2. There may be one or more metallization layers M1, V1, M2 disposed over transistors 106 and other devices formed in a workpiece 102, for example, as shown.
An insulating material layer 110a may be disposed between the transistors 106. Conductive features 116a may comprise plugs or vias that make electrical contact to a source or drain region 104 of a transistor 106, for example. Metallization layer M1 includes a plurality of conductive features 112a formed within an insulating material layer 110b disposed over insulating material layer 110a. Some of the conductive features 112a may comprise conductive lines that make electrical contact to the gates or gate contacts of the transistors 106, as shown. Other conductive features 112a may comprise plugs or vias that electrically connect conductive features 116a and 116b, as shown. Metallization layer V1 may include a plurality of vias 116b formed in an insulating material layer 110c that provide electrical connection between conductive features 112a and 112b in adjacent metallization layers M1 and M2, for example. Metallization layer M2 may include conductive features 112b that comprise conductive lines formed in an insulating material layer 110d, for example.
A top view of metallization layer M1 is shown in FIG. 2. Conductive features 112a comprise a plurality of conductive lines that have ends that reside over gate contacts 108, as shown. In some semiconductor device 100 designs, the conductive line ends make contact with two underlying contacts 108, as shown.
There is a trend in the semiconductor industry towards reducing the size of features, e.g., the circuits, elements, and conductive lines and vias, in order to increase performance of the semiconductor devices, for example. The minimum feature size of semiconductor devices has steadily decreased over time. As feature sizes diminish, patterning and alignment of conductive lines and circuit components becomes challenging.
One problem that can occur is line end shortening 116, which is shown in the cross-sectional view of FIG. 1. Variations in wafer processing may cause shortening 116 of line ends of conductive features 112b, e.g., a line end may be shortened to 114 by an amount 116, reducing the amount of overlap of conductive features 112b with an underlying vias 116b or contact (e.g., such as gate contacts 108). If the amount of line end shortening is large, there may be no overlap to an underlying via 116b or contact 108, resulting in open circuits and reduced manufacturing yields.
One possible approach to solving the line end shortening problem may be to increase the amount of overlap of conductive features to underlying vias or contacts. However, this approach has the drawback of increasing the overall size of the integrated circuit, e.g., in a lateral direction.
Another approach may be to develop more complex lithography techniques (e.g., such as the use of serifs and other lithography improvement techniques) and/or etch solutions to prevent line end shortening, for example. However, these solutions have been tried in the industry and have not been shown to adequately solve the line end shortening problem.
What are needed in the art are methods for reducing line end shortening of conductive features of semiconductor devices.